CSK6012
CSK6系列是一个双核微控制器，嵌入了一个ARM STAR核心和一个HiFi4核心。ARM Star核心是为32位微控制器应用而设计的，因此提供了高性能、低功耗、简单的指令集和寻址，以及与现有解决方案相比减少的代码大小。HiFi4核心是为音频编码器和解码器，如MP3，AAC，和FLAC。独立的NPU是为神经网络操作而设计的。CSK6系列产品适用于智能家居电器。CSK6串行可以工作高达300 MHz。因此，它可以支持各种需要高CPU性能的工业控制和应用程序。CSK6串行有一个内置的1mb数据SRAM。CSK6串行支持许多系统级外围设备功能，如IO端口、DVP、定时器、看门狗定时器、UART、SPI、I2C、DMA、PLL、USB1.1（全速）、RTC和SDIO
乐侠可根据客户需求基于CSK6012提供IC，模组和完整解决方案等多种支持。
乐侠可根据客户需求基于CSK6012提供IC，模组和完整解决方案等多种支持。
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详 细 参 数 |
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Core |
• The ARM STAR and HiFi4 dual-core operates up to 300 MHz. • Independent 128-GB NPU. Maximum speed: 300 MHz.
• Hardware multiplier and hardware divider.
• The embedded debug module supports the serial debug port (2-wire) and the JTAG debug port (4-wire).
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Memory |
• External NOR flash:
– External flash through the QSPI.
– The QSPI supports 133 MHz maximumly.
• SRAM:
– Totally 1088-KB SRAM shared by ARM and HiFi4 cores.
– Dedicated 96-KB SRAM for the NPU block.
– Maximum bandwidth: 600 MHz.
• PSRAM:
– 8-MB PSRAM.
– Maximum bandwidth: 400 MHz.
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Clock Control |
• Programmable system clock sources:
– External 24-MHz high-speed crystal input to provide reference clock for the system.
– External 32-KHz low-speed oscillator (optional).
– Internal 32-KHz low-speed oscillator with calibration.
– The PLL allows CPU operation up to 300 MHz with the system oscillator.
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IO Port |
• Up to 26 GPIO pins. • GPIO configuration.
• Quasi-bidirectional (pull-up enabled).
• Pull-down.
• Push-pull (output).
• Input only (high-impedance).
• An I/O pin can be configured as an interrupt source through edge/level configuration.
• Flexible IO function selection.
• 5-V tolerance IO for GPIOA.
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GPT |
The GPT has eight independent channels and supports four LEDC outputs and eight PWM outputs. This multi-function timer provides the following four usage scenarios depending on the configuration of the channel mode register bit. The maximum output frequency of the PWM is 50 MHz.
• Timer mode
Support 8/16/32-bit timers.
• Input capture mode
The capture count mode is used to capture the number of input pulses and the capture time mode is used to
capture pulse width.
• LEDC output mode
• PWM mode
PWM can be configured as central-aligned mode and edge-aligned mode.
– PWM output duty cycle 0% and 100%
If the duty cycle is set to 0% or 100%, the shadow register of the GPT module will not work. This will lead to pulse generation when the duty cycle is changed dynamically from zero to none-zero or from 100 to any other value.
– PWM output duty cycle error
The PWM output duty cycle error depends on the frequency out and clock select values.
Take the PWM edge-aligned mode for example:
The actual high and low periods of PWM are *1 + high period* and *1 + low period* respectively.
shows that different dividers will lead to different duty errors.
If the divider is set to 32, the real PWM clock is 100*10^6/32 and the total period PWM counter value is small (32).
If the divider is set to 8, the real PWM clock is 100*10^6/8 and the total period PWM counter value is big (125). this will greatly reduce duty errors.
If the target PWM frequency is 10 MHz and the divider is set to 1, the real PWM clock is 100*10^6/1, the total period PWM counter value is very small (10). This will greatly increase duty errors.
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SAR ADC |
• Up to three external channel inputs.
• Three internal channels (1/6 VDD, 1/8 VCC, Keysense).
• 12-bit resolution, up to 1 Msps, 24-MHz ADC clock.
• Configurable hardware ADC trigger sources.
• Configurable n-times ADC sampling.
• Dedicated ADC data FIFO for each ADC channel.
• Configurable ADC sampling duration.
• Configurable waiting time for the next round of A/D conversion.
• Switch on/off control.
• ADC trimming.
• ADC channel selection.
• External/internal VREF selection.
• Real voltage calculation:
Regadc_value = ADC register value
Voltage = (Regadc_value - 2048)/2048*3.3
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