LX8722DM

Items

Description

Processor

Dual processor core

KM4: Armv8-M architecture with Cortex-M33 instruction set compatible

KM0: Armv8-M architecture with Cortex-M23 instruction set compatible

Equal access to address space including SRAM, peripherals and registers

KM4 CPU

Cortex-M33 instruction set compatible
    Floating Point Unit (FPU)
    DSP
    TrustZone-M
Running at a frequency of up to 200MHz (configurable)
Memory Protection Unit (MPU)
Built-in Nested Vectored Interrupt Controller (NVIC)
Non-maskable Interrupt (NMI) with a selection of sources
Serial Wire Debug (SWD) with 2 HW breakpoints and 1 watchpoint (without Serial Wire Output
(SWO) for enhanced debug capabilities)
System tick timer
32KB I-Cache and 4KB D-Cache

KM0 CPU

Cortex-M23 instruction set compatible

Running at a frequency of up to 20MHz

Built-in Nested Vectored Interrupt Controller (NVIC)

Non-maskable Interrupt (NMI) with a selection of sources

SWD with 2 HW breakpoints and 1 watchpoint

System tick timer

16KB I-Cache and 4KB D-Cache

KM4 CPU On-Chip memory

Up to 512KB contiguous main SRAM @200MHz

Optional 4MB PSRAM @ 50MHz, 8-bit DDR, refer to 1.4.2

KM0 CPU On-Chip memory

Up to 64KB contiguous main SRAM

Up to 1KB retention SRAM for keeping data in power saving modes

GDMA

KM4 and KM0 both have a GDMA controller

HS-GDMA0 supports six channels with TrustZone-M

LP-GDMA0 supports six channels without TrustZone-M

Flash

Optional internal 4M bytes (32M bits) Flash, refer to 1.4.2

SPI/DSPI/QSPI1 Flash controller with cache

Flash In-Circuit Programming (ICP) supported

General-Purpose I/O (GPIO)

Up to 64 General-Purpose I/O (GPIO) pins. All GPIOs have configurable pull-up/pull-down resistors.

GPIO interrupt trigger could be configured with rising, falling or both input edges.

IPC

Inter-Processor communication